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PI6C185-00
Precision 1-7 Clock Buffer
Product Features
* High-speed, low-noise non-inverting 1-7 buffer * Switching speed up to 140 MHz (PI6C185-00A)* * Supports up to three mobile SDRAM DIMMs * Low skew (<250ps) between any two output clocks * I2C Serial Configuration interface * Multiple VDD, VSS pins for noise reduction * 3.3V power supply voltage * 20-pin TSSOP (L) and QSOP (Q) packages * Maximum Operating Frequencies: PI6C185-00 = 125 MHz; PI6C185-00A = 140 MHz.
Description
The PI6C185-00 is a high-speed low-noise 1-7 non-inverting buffer designed for SDRAM clock buffer applications. This buffer is intended to be used with the PI6C10X clock generator for Intel Architecture-based Mobile systems. At power up all SDRAM output are enabled and active. The I 2C Serial control may be used to individually activate/deactivate any of the 7 output drivers. Note: Purchase of I2C components from Pericom conveys a license to use them in an I2C system as defined by Philips.
Block Diagram
Pin Configuration
SDRAM0
VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 VDD SDRAM6 SDRAM5 VSS VDD SDRAM4 SDRAM3 VSS VSS SCLK
SDRAM1 BUF_IN SDRAM2
SDRAM0 SDRAM1 VSS BUF_IN VDD SDRAM2
SDRAM3
20-Pin L, Q
16 15 14 13 12 11
SDRAM6
VSS
SDATA SCLOCK
I2C I/O
VDD SDATA
1
PS8317A
03/22/01
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PI6C185-00 Precision 1-7 Clock Buffer
Pin Description
Pin 2,3,7,14,15,18,19 5 10 11 1,6,9,16,20 4,8,12,13,17 Signal SDRAM[0.6] BUF_IN SDATA SCLK VDD VSS Type I I I/O I Power Ground Qty. 7 1 1 1 5 5 Clock Buffer Input Serial Data for I2C interface, internal pull- up. Serial Clock for I2C interface, internal pull- up 3.3V Power Supply Ground De s cription Buffered Clock Outputs
PI6C185-00 I2C Address Assignment
A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W 0
PI6C185 Serial Configuration Map
Byte0: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 15 14 7 3 2 D e s cription SDRAM4 (Active/Inactive) SDRAM3 (Active/Inactive) NC (Initialize to 0) SDRAM2 (Active/Inactive) NC (Initialize to 0) NC (Initialize to 0) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive)
Byte1: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 19 18 D e s cription NC (Initialize to 0) NC (Initialize to 0) NC (Initialize to 0) NC (Initialize to 0) NC (Initialize to 0) NC (Initialize to 0) SDRAM6 (Active/Inactive) SDRAM5 (Active/Inactive)
Note: Inactive means outputs are held LOW and are disabled from switching
2
PS8317A
03/22/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C185-00 Precision 1-7 Clock Buffer
2-Wire I2C Control
The I2C interface permits individual enable/disable of each clock output and test mode enable. The PI6C185-00 is a slave receiver device. It can not be read back. Sub addressing is not supported. To change one of the control bytes, all preceding bytes must be sent. Every bite put on the SDATA line must be 8-bits long (MSB first), followed by an acknowledge bit generated by the receiving device. During normal data transfers SDATA changes only when SCLK is LOW. Exceptions: A HIGH to LOW transition on SDATA while SCLK is HIGH indicates a start condition. A LOW to HIGH transition on SDATA while SCLK is HIGH is a stop condition and indicates the end of a data transfer cycle. Each data transfer is initiated with a start condition and ended with a stop condition. The first byte after a start condition is always a 7-bit address byte followed by a read/write bit. (HIGH = read from addressed device, LOW = write to addressed device). If the devices own address is detected, PI6C185-00 generates an acknowledge by pulling SDATA line LOW during ninth clock pulse, then accepts the following data bytes until another start or stop condition is detected. Following acknowledgement of the address byte (0D2H), two more bytes must be sent: 1. Command Code byte, and 2. Byte Count byte. Although the data bits on these two bytes are dont care, they must be sent and acknowledged.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ......................................... 65C to +150C Ambient Temperature with Power Applied ........... 0C to +70C 3.3V Supply Voltage to Ground Potential ............. 0.5V to +4.6V DC Input Voltage .................................................. 0.5V to +4.6V Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Supply Current (VDD = +3.465V, CLOAD = Max.)
Symbol IDD IDD IDD IDD Parame te r Supply Current Supply Current Supply Current Supply Current Te s t Condition BUF_IN = 0 MHz BUF_IN = 66.66 MHz BUF_IN = 100.0 MHz BUF_IN = 133.3 MHz 85 130 220 M in. Typ. M ax. 3 mA Units
3
PS8317A
03/22/01
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PI6C185-00 Precision 1-7 Clock Buffer
DC Operating Specifications (VDD = +3.3V 5%, TA = 0C - 70C)
Symbol Input Voltage VIH VIL IIL VOH VOL COUT CIN LPIN TA Input high voltage Input low voltage Input leakage current Output high voltage Output low voltage Output pin capacitance Input pin capacitance Pin Inductance Ambient Temperature No Airflow 0 0 < VIN < VDD IOH = 1mA IOL = 1mA VDD 2.0 VSS - 0.3 -5 2.4 0.4 6 5 7 70 VDD +0.3 0.8 +5 V mA Parame te r Te s t Condition M in. M ax. Units
VDD[0-9] = 3.3V 5% V pF nH C
SDRAM Clock Buffer Operating Specification
Symbol IOHMIN IOHMAX IOLMIN IOLMAX trhSDRAM tthSDRAM Parame te r Pull- up current Pull- up current Pull- down current Pull- down current Output rise edge rate SDRAM only Output fall edge rate SDRAM only Te s t Conditions VOUT = 2.0V VOUT = 3.135V VOUT = 1.0V VOUT = 0.4V 3.3V 5% @04V- 2.4V 3.3V 5% @2.4V- 0.4V 1.5 1.5 54 53 4 4 V/ns M in. 54 - 46 mA Typ. M ax. Units
AC Timing
Symbol tSDKP tSDKH tSDKL tSDRISE tSDFALL tPLH tPHL tPZL,tPZH tPLZ,tPHZ Duty Cycle tSDSKW Parame te r SDRAM CLK period SDRAM CLK high time SDRAM CLK low time SDRAM CLK rise time SDRAM CLK fall time SDRAM Buffer LH prop delay SDRAM Buffer HL prop delay SDRAM Buffer Enable delay SDRAM Buffer Disable delay Measured at 1.5V SDRAM Output to Output Skew 66 M Hz M in. 15.0 5.6 5.3 1.5 1.5 1.0 1.0 1.0 1.0 45 4.0 4.0 5.0 5.0 8.0 8.0 55 250 M ax. 15.5 100 M Hz M in. 10.0 3.3 3.1 1.5 1.5 1.0 1.0 1.0 1.0 45 4.0 4.0 5.0 5.0 8.0 8.0 55 250 M ax. 10.5 133.3 M Hz M in. 7.5 2.2 2.0 1.4 1.4 1.0 1.0 1.0 1.0 45 4.0 4.0 5.0 5.0 8.0 8.0 45 250 % ps ns V/ns M ax. 8.0 ns Units
4
PS8317A
03/22/01
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Output Buffer Test Point Test Load
PI6C185-00 Precision 1-7 Clock Buffer
tSDKP tSDKH
3.3V Clocking Interface (TTL)
2.4 1.5 0.4
tSDKL tSDRISE tSDFALL
Input Waveform tplh Output Waveform
1.5V
1.5V
tphl
1.5V
1.5V
Figure 1. Clock Waveforms
Minimum and Maximum Expected Capacitive Loads
Clock SDRAM M in. Load M ax. Load Units 20 30 pF Note s SDRAM DIMM Specification
Notes: 1. Maximum rise/fall times are guaranteed at maximum specified load. 2. Minimum rise/fall times are guaranteed at minimum specified load. 3. Rise/fall times are specified with pure capacitive load as shown. Testing is done with an additional 500 resistor in parallel.
Design Guidelines to Reduce EMI
1. Place series RS resistors and CI capacitors as close as possible to the respective clock pins. Typical value for CI is 10pF. RS Series resistor value can be increased to reduce EMI provided that the rise and fall time are still within the specified values. 2. Minimize the number of vias of the clock traces. 3. Route clock traces over a continuous ground plane or over a continuous power plane. Avoid routing clock traces from plane to plane (refer to rule #2). 4. Position clock signals away from signals that go to any cables or any external connectors.
5
PS8317A
03/22/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C185-00 Precision 1-7 Clock Buffer
PCB Layout Suggestion
C1
C5
VDD
1 2 3
20 19 18 17 16 15 14 13 12 11
VDD
FB
VDD
VSS
C2
4 5
VSS VDD
C4
C6 22F
VDD VSS VDD
6 7
C3
8 9 10
VSS VSS
Via to VSS Plane Via to VDD Plane Void in Power Plane
Note: This is only a suggested layout. There may be alternate solutions depending on actual PCB design and layout. As a general rule, C1-C5 should be placed as close as possible to their respective VDD.
Recommended capacitor values: C1-C5 .............. 0.1F, ceramic C6 .................. 22F
From Chipset
PI6C185
7
Rs CL
SDRAM DIMM Spec.
Figure 2. Design Guidelines
6
PS8317A
03/22/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C185-00 Precision 1-7 Clock Buffer
20-Pin TSSOP Package Mechanical (L)
20
.169 .177
4.3 4.5
1 .252 .260 6.4 6.6 .004 0.09 .008 0.20 .047 1.20 Max 0.45 0.75 .018 .030
SEATING PLANE
.238 .269 6.1 6.7
.0256 BSC 0.65
.007 .012 0.19 0.30
.002 0.05 .006 0.15
X.XX X.XX
DENOTES CONTROLLING DIMENSIONS IN MILLIMETERS
20-Pin QSOP Package Mechanical (Q)
20
.150 .157
3.81 3.99 .015 x 45 0.38
1 .337 8.56 .344 8.74 .016 .050 .053 1.35 .069 1.75 SEATING PLANE 0.41 1.27 .007 .010 0.178 0.254
.058 REF 1.47
.228 .244 5.79 6.19
.025 BSC 0.635
.004 0.101 .010 0.254 .008 0.203 .012 0.305 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
Ordering Information
P/N PI6C185- 00L PI6C185- 00Q PI6C185- 00AL PI6C185- 00AQ M ax. Fre q. 125 MHz 125 MHz 140 MHz 140 MHz Package 20- Pin TSSO P Package 20- Pin Q SO P Package 20- Pin TSSO P Package 20- Pin Q SO P Package
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
7
PS8317A 03/22/01

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